Typical dynamic random access memory (DRAM) controllers follow a specific sequence to access a memory location. This sequence includes activating or opening a bank of memory, accessing (e.g., reading or writing) a memory location in the bank of memory, and closing or precharging the bank of memory. Generally, each step of the sequence is the result of an individual explicit command. When multiple memory locations within a single bank of memory are accessed, the activation and precharging steps can be performed once for the group of accesses to the bank of memory.
Many computer systems have multitasking capabilities that allow the computer system to maintain multiple active processes. Because processes often access memory locations within a common bank of memory, the activation and precharging steps can be performed sparingly for a single process. When multiple processes are active, however, each process has a location in memory that can be repeatedly accessed. Thus, the activation and precharging of DRAM banks are often included in context switching overhead.
What is needed is a method and apparatus that reduces the number of precharge operations in a memory sub-system having multiple banks.